CTE-Matched Substrate & Plating Selection for High-Temp PCBs

In high-temperature environments (>150℃), CTE mismatch causes plating cracks and solder joint failures. A Z-axis CTE difference >5ppm/℃ leads to 90% solder crack risk after 200 thermal cycles (-55℃~175℃). This guide details selection strategies through material analysis, matching models, and validation data.

1. CTE Mismatch Mechanisms

1.1 Thermal Stress Model

Interlayer stress (σ):

Where:

• $E$: ElastIC modulus (GPa)

• $\nu$: Poisson's ratio

• $\mathrm{<br>}\mathrm{<br>}$: CTE difference (ppm/℃)

• $\Delta T$: Temperature swing (℃)
  Critical Threshold: Microcracks form when $\sigma$ > 120MPa

1.2 Failure Modes

2. Substrate Selection

2.1 High-Temp Material CTE

2.2 Substrate-Plating CTE Matrix

3. Plating Optimization

3.1 Composite Plating Structure (Fig.2)

PTH Hole Solution:

1. Electroless Ni: CTE 13.5ppm/℃ (8wt% P)

2. Transition Layer: Nanocrystalline Ni (CTE 10.5ppm/℃)

3. SuRFace Layer: Hard Au (CTE 14.2ppm/℃)
   Result: Z-axis CTE gradient <3ppm/℃

3.2 Key Process Parameters

4. Validation & Case Study

4.1 Thermal Cycling Data (-55℃↔175℃)

4.2 Mars Rover PSU Module

• Environment: -120℃~+125℃ (Diurnal Cycle)

• Materials:

  • Substrate: Ceramic-Filled PTFE (Z-CTE=28ppm/℃)

  • Plating: Ni/Hard Au Composite (CTE=12.8ppm/℃)

• Results:

  • PTH Resistance Change <2% after 3000 cycles

  • Zero Microcracks (SEM, Fig.3)

5. Selection Flowchart