Layer-to-Layer Signal Routing Planning in 4-Layer PCBs: A Comprehensive Analysis

Abstract: Signal layer planning in 4-layer PCBs critICally impacts signal integrity (SI), EMC, and crosstalk control. The core principle is "orthogonal routing between adjacent signal layers" (e.g., top layer horizontal, bottom layer vertical), combined with solid reference planes and the 20H rule for impedance control and crosstalk suppression. This article details the planning strategy and technical basis.

1. Standard Stackup & Layer Assignment

Design Redlines:

• L1 and L4 must be orthogonal (90° cross); minimize parallel routing.

• L2/L3 planes must remain solid (no splits under high-speed signals).

2. Signal Routing Principles

1. Orthogonal Routing Rule:

   • If L1 routes at 0° (horizontal), L4 must be 90° (vertical);

   • Parallel segments ≤15mm (prevents ↑30% crosstalk); spacing ≥3W (W=trace width).

2. Layer Transition Handling:

   • Add GND vias (≥0.2mm hole) within 5mm of transition points;

   • Never route L1→L4 directly; transition through L2/L3 reference planes.

3. Critical Signal Strategies

1. High-Speed Signals (>50MHz):

   • Prioritize L1 (top layer); avoid crossing splits (if unavoidable, spacing ≥3mm);

   • Guard traces: Add GND shields on both sides (spacing 2W); GND vias every 20mm.

2. Clock Signals:

   • Route on L1 referenced to L2 GND; length matching tolerance ±0.1mm;

   • No >10mm parallel runs with high-speed signals.

3. Differential Pairs:

   • Intra-pair spacing =2W; inter-pair spacing ≥5W;

   • Synchronous layer transitions; via spacing ≤0.3mm (minimizes phase skew).

4. Power/Ground Plane Management

1. Plane Splitting:

   • Spacing between voltage domains ≥0.5mm (e.g., 3.3V/5.0V);

   • Avoid parallel runs with signals (angle ≥45°).

2. 20H Rule:

   • Power plane (L3) recessed by 20×dielectric thickness (20×0.15mm=3mm) from GND (L2) to reduce edge radiation.

3. Decoupling Capacitors:

   • Place within ≤1.5mm of IC power pins; GND terminals directly connected to L2 plane (via ≤0.5mm away).

5. EMC & SI Optimization

1. Crosstalk Control:

   • Orthogonal routing reduces crosstalk by 10–15dB vs. parallel routing;

   • Spacing ≥5mm between sensitive signals (reset, analog) and noise sources (switchers).

2. Impedance Continuity:

   • Top/bottom (L1/L4) microstrip impedance:

     （h: dielectric thickness, w: width, t: Cu thickness, ε_r: Dk）

   • Internal striplines require symmetric stackup calculation.

3. Termination:

   • Add source-end 33Ω series resistor for >100MHz signals to suppress ringing.

6. Verification & Simulation

1. Stackup Impedance Simulation:

   • Use Polar SI9000 for line width (FR-4, ε_r=4.2):

     • L1 50Ω microstrip: w=0.26mm (h=0.15mm)

     • Internal 100Ω diff-pair: w=0.12mm, s=0.1mm

2. Crosstalk Simulation:

   • Near-end crosstalk NEXT≤-40dB for 15mm parallels (HyperLynx verification).

3. Return Path Check:

   • No gaps >0.1mm in reference plane under layer-transition signals.

Conclusion

4-layer PCB signal routing demands strict adherence to "orthogonal routing + solid reference planes":

• L1 and L4 must cross orthogonally; parallel segments ≤15mm;

• L2/L3 must be solid; split spacing ≥0.5mm with 20H rule;

• Critical Measures:

  • Route high-speed signals on outer layers,

  • Add GND vias within 5mm of layer transitions,

  • Avoid 0° angles between power splits and signals.